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jpeg_encoder
- JPEG 编码器IP核，用verilog语言编写，不支持二级采样。-JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
VITERBI
- viterbi编码算法verilog实现-viterbi encoder, developed by verilog language
Lab7_pencode83
- 8-3优先编码器的设计与实现.8-3优先编码器的真值表，本实验中用Verilog语句来描述.-Design and implementation of 8-3 priority encoder.8-3 priority encoder truth table, use the Verilog statement in this experiment to describe.
conv_encoder
- TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code
tcm_enc
- 用Verilog实现（2,1,2）卷积码和8—PSk调制相结合的TCM编码器-Using Verilog realize (2,1,2) convolutional code and 8-PSk modulation encoder combination of TCM
CAVLC
- verilog code for cavlc encoder
huff
- huffman encoder in verilog
8B_10BENCODER
- 基于8B10B的编解码模块的设计，使用verilog HDL语言，具有实用价值。-8B10B encoder
Haffman-encoding
- verilog implementation of huffman encoder with testbench
des.tar
- DES Encoder and Decoder Verilog RTL Code
HDB3-encoderauncoder
- HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现-HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
RS_enc
- RS编码器设计，使用Verilog实现。-RS encoder design, Verilog implementation.
1553-EncoderDecoder---Documentation
- 1553b编解码参考设计 verilog 收发-1553b encoder decoder
Encoder_8X3
- verilog code of 8X3 Encoder.
RS_255_223_ENCODER
- rs255编码解码器，verilog描述，FPGA实现-RS255 223 ENCODER
cycle_en_decoder
- 卷积码编码/解码，Verilog语言实现，带仿真程序。-Convolution encoder/decoder, Verilog language, with a simulation program.
demoss
- FPGA的代码verilog语言编写，包括LED与按键验证，数据选择器，编码器，译码器半加器，全加器，适合初学者，已经在板子调试成功，板子是 睿智IV开发板。-FPGA code verilog language, including LED and key authentication, data selection, encoder, decoder and a half adder, full adder, suitable for beginners, it has been succe
H.264-for-FPGA
- This Book describe about H.264 encoder using Verilog HDL